-----------------------------------------------------------------------------------
--|
--| Filename:     fpga_dac.vhd
--|
--| Contents:     Entity          :  dac
--|               Architecture    :  dac_rtl
--|
--| Description:  The program is 
--|               
--|               
--|               
--|
--| Author:       C. Talsma (derived from Xilinx AppNote XAPP154, Sept, 1999)
--|
--| Version:      1.0
--|
--| Revision History:
--|   Date:    
--|   By:    
--|   Change:
--|
--|
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


entity dac is
port(
    RESET    : in  std_logic;
    CLOCK    : in  std_logic;
    DAC_IN   : in  std_logic_vector (15 downto 0);
    DAC_OUT  : out std_logic
);
end dac;

architecture dac_rtl of dac is
    
    signal delta_adder : std_logic_vector (17 downto 0);
    signal delta_addb  : std_logic_vector (17 downto 0);
    signal sigma_add   : std_logic_vector (17 downto 0);
    signal sigma_latch : std_logic_vector (17 downto 0);

begin

get_addb : process (sigma_latch)
begin 
	delta_addb  <= sigma_latch(17) & sigma_latch(17) & "0000000000000000";      
end process get_addb;

get_delta : process (DAC_IN, delta_addb)
begin
	delta_adder <= DAC_IN + delta_addb;
end process get_delta;

get_sigma : process (sigma_latch, delta_adder)
begin
	sigma_add   <= sigma_latch + delta_adder;
end process get_sigma;
    
data_out : process (CLOCK, RESET)
begin
  
	if RESET = '1' then 
        sigma_latch <= "100000000000000000";
        DAC_OUT     <= '0';
        
    elsif rising_edge (CLOCK) then
        sigma_latch <= sigma_add;
        DAC_OUT     <= sigma_latch(17);
        
    end if;
end process data_out;    
 
end dac_rtl;  
                     













